A 1-V 225-nW 1KS/s current successive approximation ADC for pacemakers

An ultra-low-power 1KS/s 8-bit current mode successive approximation (SAR) analog-digital converter (ADC) for pacemakers is presented. The proposed system architecture is designed to achieve a small chip area and ultra low power consumption by using current mode operation. The circuit is realized in a IBM 0.13μm CMOS technology. The simulated power consumption is 225 nW corresponding to a figure of merit of 0.657pJ/conversion-step while operating from a 1 V supply. The power consumption is one of the lowest reported.