A high output voltage swing logarithmic image sensor designed with on chip FPN reduction

A novel architecture of a CMOS image sensor dedicated to improve the output voltage swing of a simple logarithmic sensor, while conserving the simplicity and then the minimized area of the normal sensor, is proposed. This architecture presents a reduced fixed pattern noise (2.1%) and a good signal to noise ratio (60dB). The sensor has been designed in 0.35μm, 3.3V standard technology and the pixel measures (11.7×11.7μm
²
) with a Fill Factor about 26%. The output voltage swing expected is improved by almost a factor of 2.3 compared to the voltage swing of the typical logarithmic sensor, with a 120dB dynamic range.