Hardware and software synthesis of image filters from CAL dataflow specification

Image filtering is mainly used for pre-processing in many applications of image processing such as noise removal in industrial inspection, enhancement for pattern recognition, restoration of degraded images, etc. For real-time processing, it is crucial that these applications meet the desired throughput. As processing demands get higher through complex algorithms and large resolution or very high frame rate images, general purpose computers can no longer sustain the required time. Hardware implementation on the other hand, though capable of producing high performance design, is often considered difficult and time consuming to perform due to the low abstraction level. This paper presents an efficient dataflow architecture for image filtering which allows rapid design implementation with features such as the Region of Interest, Memory Cache, and Border Replication. For parallel processing, dataflow Token Splitting technique is also applied, which provides a simple way to increase data throughput. Furthermore, the capability to synthesize CAL dataflow program to both hardware and software provides a platform for co-design of complex image processing systems. Experimental results from synthesis of four different types of filters show that parallel image filtering with a factor of four is up to 3.5 times faster on FPGA compared to sequential processing on single core general purpose processor, with additional slice of only 2% from single to four parallel filters.