VLSI array architectures for pyramid vector quantization

We present parallel algorithms and array architectures for pyramid vector quantization (PVQ) for use in image coding in low-power wireless systems. Both encoding and decoding algorithms have data-dependent iteration bounds and data-dependent dependencies which prevent efficient parallelization of the algorithms. We perform an algorithmic transformation to convert data-dependent regular algorithms to equivalent data-independent regular algorithms. The resulting regular algorithms exhibit modular and regular structures; hence, they are well suited for VLSI array implementation. Based on our parallel algorithm and systematic design methodologies, linear array architectures have been developed. Both encoder and decoder architectures consist of L identical processors with local interconnections and provide O(L) speedup over a sequential implementation, where L is the dimension of a vector. The architectures achieve 100% processor utilization and permit power savings through early completion detection.