Optimizing the process window of Bond Line Thickness for Printable Die Attach Adhesive in DDR DRAM packaging

The mainstream in DDR DRAM packaging is the face down substrate-on-chip (SOC) configuration using Printable Die Attach Adhesives (PDAA). PDDA have been developed that deliver the performance of a film with the low cost of a paste. PDDA are stenciled onto the substrate and the subsequent processes included B-cure, die bonding, and C-cure will reduce the adhesives thickness by removing the solvent and leaving only solid adhesive resins behind. The shrunk adhesive thickness between the chip surface and the substrate is named as Bond Line Thickness (BLT). Thinner BLT accounts for the majority of assembly defects, and most defects are originated from poor understanding of the effect of process parameters and the nature of their interactions. When BLT's margin is not enough, the bigger fillers of PDAA will damage chip surface. It will affect manufacturing lead times, product and process costs, process yields, product quality, and customer satisfaction. This study concerns the determination of BLT process windows for PDAA. The key process parameters considered in this study are printing pressure, printing speed, bonding force, bonding temperature, and stencil thickness. To overcome this challenge, this study applies 6 sigma DMAIC approach and proposes a novel application of Response Surface Methods (RSM), which could meet the purpose of the tolerance design, by means of using the curvature correlations among significant factors. According to above analysis, the curvature relationships among the significant factors (bonding temperature, bonding force, and printing pressure) are obtained to control the BLT's margin and to illustrate process windows for them simultaneously. After implementing these process windows, the BLT's Cpk is improved from -0.43 to 1.76 and the testing failure rate is reduced about 2000 ppm.