A universal technique for accelerating simulation of scan test patterns

Scan test patterns are typically generated by ATPG tools which use a zero delay simulation model. These scan test patterns have to be verified using a golden simulator which is approved by the chip foundry with full timing before the patterns are accepted for manufacturing test. This can be very time consuming for many designs because of the size of the test data and the large number of test cycles which have to be simulated. A universal technique for accelerating scan test pattern simulation which can be used for any simulator with any scan cell type from any foundry is proposed. The extensions to test data languages to support universal acceleration of scan pattern simulation are also proposed. Some experiment results are also provided.