CMOS inverter design-hardened to the total dose effect

This paper reports and discusses the experimental behavior of two inverter structures Rad-Hardened by Design to /sup 60/Co irradiation. We use the results on a set of basic circuits and transistors exposed to the same total doses as these structures to establish the effective formation conditions of the parasitic channel. Then this leakage evolution is related to the gate voltage history under irradiation. Finally, we take advantage of this intrinsic degradation property to propose a new Design Rad Hardened (DRH) cell. This structure considerably limits the Low Noise Margin degradation, helps to maintain the logic functionality with a High Output level and improves both the rad-tolerance and the static power consumption.