70% read margin enhancement by VTH mismatch self-repair in 6T-SRAM with asymmetric pass gate transistor by zero additional cost, post-process, local electron injection

A V
_TH
mismatch self-repair scheme in 6T-SRAM with asymmetric PG transistor by post-process local electron injection is proposed for the first time. The asymmetric V
_TH
shift is doubled from the conventional scheme without process and area penalty. Measurement results show 24% increase in SNM without write degradation by the asymmetric PG transistor. 70% read margin enhancement is achieved by the proposed scheme.