High-speed comparator used for high-speed, high-resolution A/D converter

Based on the application of high-speed, high-resolution A/D converter, this paper describes the design and implementation of a novel high-speed comparator. The comparator uses the high-speed, transmission delay stability technology, the auto-zero technology, and the cascade technology in order for the comparator to have the high-speed, high-resolution, transmission delay stability features. Its performances are verified by a 14-bit 125MSPS pipelined A/D converter which is developed in 0.35 μm CMOS-based process technology. The SFDR of the A/D converter is up to 87 dB at an input clock of 125 MHz with an input signal of 10 MHz.