A 2.5MS/s 225 µW 8-bit charge redistribution SAR ADC for multichannel applications

This paper presents a design of integrated analog-to-digital converter implemented in UMC CMOS 180nm technology dedicated to multichannel readout circuits. The successive approximation architecture with charge redistribution was proposed. A capacitive DAC is presented, where CMOS switches are described in detail in terms of speed and accuracy. In order to reduce the DAC's area, a resistive auxiliary sub-DAC is also presented. A synchronous 30 MHz latch with preamplifier is used as a comparator. Designed ADC achieves conversion rates of 3 MS/s at 225 μW. Final simulation results indicate low nonlinearity of 0.3 LSB of the presented circuit.