Stackable short flow Characterization Vehicle test chip to reduce test chip designs, mask cost and engineering wafers

Being successful in semiconductor manufacturing is increasingly challenging for sub 100 nm technology nodes. Typically, 10+ test chips have been used to develop and ramp a new technology, which cannot be sustained considering that mask cost alone are up to 10 times higher today than in pre-OPC days. At the same time, design rules are more and more complex demanding more experiments and thus more test chip area to characterize a technology. In short, more and more experiments have to be packed into less test chip area, while reducing overall test time and increasing learning cycles. A Stackable Characterization Vehicle
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test chip will be presented that combines several test chips into ONE single mask set to reduce overall mask cost. Since experiments are stacked on top of each other over several layers, wafers can be reused for multiple runs to reduce the number of engineering wafers within a fab. Furthermore, these can be tested on an ultraparallel tester, reducing test overhead.