New integrated architecture for H.264 Transform and Quantization hardware implementation

Due the computational complexity of video processing algorithms the practical implementation of modern video encoders, like H.264/SVC, normally demands for some kind of hardware acceleration. In this paper we present a new integrated computational hardware module, able to perform the H.264 encoder algorithms of Discrete Cosine Transform, Hadamard Transform and Quantization. All these hardware modules were jointly designed aiming to speed up encoder performance by optimizing timing synchronism, data handling and memory accesses. Particularly our integrated solution globally allows the complete processing of up to eight samples by clock of distinct data types (luma, blue or red chroma) for both inter or intra operations. The proposed project has been implemented for logic programmable technology using hardware description language (VHDL). Practical results obtained after synthesing and downloading the proposal into commercial FPGA boards confirms it as an innovative high performance hardware solution, adequate for real-time encoder implementation.