The multi-rate Iterated Timing Analysis algorithm for circuit simulation

In circuit simulation, Relaxation-based algorithms have been proven to be faster and more flexible than the standard direct approach used in SPICE. ITA (Iterated Timing Analysis) algorithm has even been widely used in industry. This paper describes accelerating techniques that enable ITA to utilize circuits' multi-rate behaviors. These techniques are based on the latency property of subcircuits and the Strength of Signal Flow (SSF) between subcircuits. A more powerful technique using both latency and SSF is also proposed. Experimental examples are given to justify the superior properties of proposed methods.