Integrated read assist-sense amplifier scheme for high performance embedded SRAMs

Embedded memories have become a dominant block in modern SOCs and often constitute more than half the die area. Sense amplifiers are crucial circuits in memories as they are largely responsible for the read operation. The scaling of CMOS technology deep into the sub-micron range has created numerous challenges for SRAMs; notably in that conventional sense amplifier architectures suffer from mismatch and process variability. This paper presents a novel sensing schemes featuring a read assist circuit that enhances the SRAM cell operation and robustness. Schematic and post layout simulation results show a 60% speed improvement and 62% power saving as compared to conventional sensing schemes.