Optimized BIST for embedded dual-port RAMs

This paper describes new optimal test pattern generation algorithms for embedded dual-port random access memories (DPRAMs) which have two independent read-write ports. They are widely used in networking and communications integrated circuits (IC). The widely available standard extensions of March algorithms for DPRAMs are not guaranteed to detect certain inter-port coupling faults which are explained in here. This paper describes a novel optimal test method using March test algorithms that also cover such faults efficiently.