Interface controlled IDP process technology for 0.3 /spl mu/m high-speed bipolar and BiCMOS LSIs

The in-situ phosphorus-doped polysilicon (IDP) emitter technique has been developed to form narrow and flat emitter region. One major problem to form the IDP process was found to be h/sub FE/ fluctuation control. We revealed the cause and mechanism of the h/sub FE/ variation and indicated the effective method of improving the device characteristics. It is concluded that the polySi/Si interface condition affects crystallization process of amorphous-silicon to polysilicon, which results in a change of stress at the emitter layer.