Instruction scheduling using genetic algorithm with taboo search for TTA-like processors

This paper presents an efficient instruction scheduling method for configurable processors based on Transport Triggered Architecture (TTA). The genetic algorithm is used to realize the instruction scheduling while the taboo search is integrated to prevent from getting into the locally optimal solution. Experiment on a serial of DSP applications shows that the proposed method can increase instruction-level parallelism (ILP) about 8.3% than the genetic algorithm alone, and 12.0% than the list scheduling method.