Hardware implementation of a fast FIR filter with residue number system

In this paper, we focus on hardware implementation of digital FIR filter. Since filtering computations have several additions and multiplications, taking advantage of residue number system (RNS) may lead to a considerable improvement in such systems. The limited inter-moduli carry propagation and parallel computations make residue number system desirable for add/multiply intensive application. In order to achieve maximum possible performance, after a comprehensive survey on RNS arithmetic units we have selected best ones for {2
ⁿ
-1, 2
ⁿ
, 2
ⁿ
+1} moduli-sets. Moreover, in the structure of proposed FIR filter the best previous designs for adders and multipliers are customized and failures of converter are mended. We have simulated and synthesized the proposed structure with VHDL and checked correctness of design via running random tests on the corresponding codes. The synthesis results show the proposed filter is fastest and in comparison with many state-of-the-arts designs.