Data link design using a time-based approach

A time-based approach to SerDes data transfer is described. As proof of concept, 2-bit 800 Mbps and 3-bit 1.2 Gbps time-based serial links have been designed and implemented using an Altera transceiver signal integrity development FPGA kit. The eye diagram of both the transmitted signal and the signal at the end of a 40-inch FR4 trace have been measured and compared for both links. The transmitted code has been successfully recovered at the receiver side.