A pipelined analog-to-digital converter using incomplete-settling-without-slewing technique

A pipelined analog-to-digital converter (ADC) using an incomplete-settling-without-slewing technique is proposed and verified by SPICE simulations. Our analysis shows that operational amplifiers (opamps) in multi-bits stages can avoid slewing and linearly settle for whole period of amplification. If opamp does not experience slewing, the error caused by incomplete settling can be regarded as a constant gain error, which can be compensated by linear digital calibration scheme. This technique not only can reduce the power consumption of the opamp by relieving its bandwidth and gain requirements, but also can decrease the convergence time of digital calibration algorithms by employing a simple linear calibration scheme. The prototype 11-bit 200-MS/s ADC is designed in TSMC's 0.13um 1P8M process. First stage is designed with insufficient bandwidths and followed by a complete-settling stage and a 9-bit ideal ADC. The SPICE simulation results show the power consumption in the first two stages is 29mW and an effective-number-of-bits (ENOB) is improved from 5.73 bits to 10.83 bits by linear digital calibration within 40,000 iterations.