Single Miller compensation using inverting current buffer for multi-stage amplifiers

A novel single Miller frequency compensation topology utilizing a current mirror as an inverting current buffer (SMCICB) for multi-stage amplifiers is proposed. An effective method for accurate placement of the Left-Half-Plane (LHP) zero, introduced by the current buffer is detailed. The SMCICB network effectively cancels the pole at output node, resulting in a single-pole system. This topology does not introduce additional transistors and static power dissipation. As a design example, we simulated a four-stage amplifier driving a 25kΩ//125-pF load, achieving 8.2MHz gain-bandwidth product, with 80 μA of quiescent current and ±1.5 V power supplies in a 0.5 μm ON Semi 2P3M process CMOS. Simulation results, in good agreement with theoretical analysis, validate the proposed SMCICB scheme.