Merged Digitally Controlled Oscillator and Time to Digital Converter for TV band ADPLL

In this paper we present a merged Digitally Controlled Oscillator DCO and Time To Digital Converter TDC architecture. The DCO is a nine-stage interpolative ring made by NOR cells. It is designed for TV applications and it is implemented in 65nm CMOS process. The oscillator has a large frequency range, from 50MHz to 500MHz, and a 28 × 39/μm
²
core area. It consumes 1mA from 1.2V power supply, and it has -120dBc/Hz@5MHz phase noise for 420 MHz carrier frequency. The oscillator states are directly used to measure the delay between input and output clocks. The resulting TDC is compact, very economic in power consumption and it has a resolution that is equal to 1/18 of the oscillation period. The DCO and the TDC are used in an All Digital Phase Locked Loop ADPLL.