Variation-aware gate sizing and clustering for post-silicon optimized circuits

As technology is aggressively scaled, nano-regime VLSI designs are becoming increasingly susceptible to process variations. Unlike pre-silicon optimization, post-silicon techniques can tune the individual die to better meet the power-delay constraints. This paper proposes a variation-aware methodology for the simultaneous gate sizing and clustering for post-silicon tuning with adaptive body biasing. The proposed methodology uses an accurate table look-up model and fully explores the interaction between gate sizing and optimal body bias based clustering. In addition, it is suitable for industrial test cases with tens of thousands gates. Our optimization methodology includes a body bias distribution alignment strategy to mitigate the impact of critical gates. In this way, the cluster's body bias voltage is not simply determined by only a few critical gates. We also prove the linear dependence between the mean of the body bias probability distribution and the gate size. Based on this, we further investigate a simultaneous sizing and re-clustering algorithm for better leakage savings. A circuit re-balancing and gate snapping scheme is then suggested to map the solution to a standard cell library. Compared with arecently-reported method, the proposed methodology can obtain on average 25.5% leakage saving at nearly the same run time.