Designing 3.125 GHz bang-bang PLL for Clock Recovery in 6.25 Gbps Backplane Communication Receiver

A 3.125 GHz Clock Recovery (CR) circuit used in the 6.25Gbps SerDes for Backplane Communication Receiver is described. Bang-bang PLL architecture is utilized for its high operation speed. An Alexander phase detector (PD) and a LC voltage-control oscillator (VCO) are involved in the circuit. The behavior of the nonlinear bang-bang PLL is modeled to give approximate evaluation of the loop stability. The circuit has been implemented in a standard 0.18 μm CMOS technology. The test result indicates that the frequency of the VCO is from 3 GHz to 3.35 GHz, the voltage gain is 270 MHz/V, and the phase noise is -118.38 dBc/Hz @1 MHz. The chip consumes less than 81 mW with 1.8 V power supply, and occupies 0.5 mm
²
area.