Non-uniform clock mesh optimization with linear programming buffer insertion

Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. However, this robustness costs power. In this work, we present a mesh edge displacement algorithm that is able to reduce mesh wire length by 7.6% and overall power by 10.5% with a small mean skew improvement. We also present the first non-greedy buffer placement and sizing technique using linear programming (LP) and iterative buffer removal. We show that compared to prior methods, we can obtain 41% power reduction and an 27ps mean skew reduction on average when variation is considered compared to prior algorithms.