A 800 /spl mu/A, 105 MHz CMOS crystal-oscillator digitally trimmable to 0.3 ppm

A 105 MHz crystal oscillator consuming 800 /spl mu/A at 1.7 V supply is described. The oscillator is part of a regulated system in a wireless device where the oscillation frequency is controlled digitally. This digital trimming of oscillation frequency is realized by binary capacitor banks of 10-bit resolution. The oscillator can be pulled from /spl plusmn/35 ppm to the required frequency with 0.3 ppm accuracy. The circuit has been fabricated in a 1 /spl mu/m CMOS technology. The measured phase noise is -100 dBc/Hz at 100 Hz offset.