Methods to enhance the performance of Iterated Timing Analysis algorithm

In circuit simulation, Relaxation-based algorithms have been proven to be faster and more flexible than the standard direct approach used in SPICE. ITA (Iterated Timing Analysis) algorithm has even been widely used in industry. This paper describes a new accelerating technique using the latency property of subcircuits and other accelerating methods based on Strength of Signal flow (SSF) for ITA algorithm. The definition of SSF, calculation method, and methods to utilize SSF all have been illustrated clearly. Experimental examples are given to justify the superior property of these proposed methods. A more powerful strategy for enhancing ITA is also designed and carefully justified.