Low power 4-bit full adder cells in subthreshold regime

In this work, low power 4-bit adder cells based on subthreshold logic in nanometer CMOS technology is presented. Twelve different subthreshold 1-bit full adders are used for designing 4-bit adders in two different topologies. These topologies are Carry-Ripple and Carry Look-Ahead adders. To compare these adders, HSpice simulations in 65nm and 90nm standard CMOS technologies are used. Different performance parameters of the adder including power, delay, power-delay product and energy-delay product as a function of supply voltage, transistor sizing, frequency, technology, and temperature are investigated. The best adder with the smallest power and power-delay product and the highest achievable frequency is determined.