Improvement of noise tolerance analysis in deep-submicron low voltage dynamic CMOS logic circuits

Dynamic CMOS logic circuits are widely employed for improved performance of VLSI chips. However, dynamic CMOS circuits are less resistant to noise than static CMOS circuits. We have given an overview of previous techniques employed for improving noise tolerance and then compared these techniques with the proposed techniques. The average noise threshold energy (ANTE) and the Energy normalized ANTE metrics have been used to quantify the noise immunity and power consumption improvement. A 2 input AND gate has been designed using the proposed techniques. Then a comparison analysis has been carried out by realizing and simulating the logic circuits in 180nm and 90nm technology at supply voltages of 1.8V and IV respectively. At 180nm technology the ANTE and Energy normalized ANTE are improved by 7.14X and 4X while for 90nm technology the ANTE and Energy normalized ANTE are improved by 1.88X and 1.65X over the conventional domino logic circuit for the proposed technique.