Architecture Design of Reconfigurable Accelerators for Demanding Applications

This paper focuses on mastering the architecture development of reconfigurable hardware accelerators for highly demanding applications. It presents the results of our analysis of the main issues that have to be addressed when designing accelerators for demanding applications, when using as an example the accelerator design for LDPC decoding for the newest communication system standards. Based on the results of our analysis, we formulate the main requirements that have to be satisfied by an adequate methodology of reconfigurable accelerator design for highly demanding applications, and propose an architecture design methodology which satisfies these requirements.