Design challenges of thermal margining tools for silicon validation

Rapid advances in the semiconductor process technology have led to miniaturization of transistor features and advent of multi-core architecture. At the silicon-level while bus speeds, features and functionalities are increasing, at the system-level, there is a steady and incessant trend of volume reduction, compact component placement on the board and noise reduction. Thermal margining tools (TTs) based on a Peltier type thermo-electric-cooler (TEC) replace the cooling solution of the device under test (DUT). The thermal margining head is controlled by the thermal controller to provide a temperature set-point based on the DUT's case temperature. These TTs provide temperature margining capability of varying the case temperature from 5°C to 100°C at silicon thermal design power (TDP) are used for process, voltage, temperature, frequency (PVTF) testing, debug, acceleration of fault detection by Intel's post-silicon validation customers across servers, desktops, mobile and graphics segments. This paper presents the thermo-mechanical design challenges of thermal margining tools. First, we present the details of the thermal margining head design for CPU, chipset and ASIC including the retention design for socketed/soldered down silicon as necessary. Second, we demonstrate how introduction of CFD modeling and retention design methodology has helped with the design optimization of the thermal head. This detailed methodology enabled designing and delivering thermal tools with predictability of the temperature margining range and improved quality of products delivered to validation customers while achieving significant cost saving of the tools. Third, we present the field issues, thermal performance degradation and failure modes of these thermal tools. Finally, we present the challenges ahead of us and the advancements we need from the rest of the industry specifically in TEC technology in designing small form factor thermal margining tools to address the shrinking KOV of the Silicon component placements on the board across the market segments to enable increasing bus speeds, features, functionalities and TDP/power density.