Heat-removal performance scaling of interlayer cooled chip stacks

Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize the performance of a three tier chip stack with a footprint of 1 cm
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. The implementation of 100 μm pitch area array interconnect compatible heat transfer structures results in a maximal junction temperature increase of 54.7 K at 1bar pressure drop with water as coolant for 250 W/cm
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hot-spot and 50 W/cm
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background heat flux. The total power removed was 390 W which corresponds to a 3.9 kW/cm
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volumetric heat flow. An efficient multi-scale modeling approach is proposed to predict the temperature response in the complete chip stack. The experimental validation confirmed an accuracy of +/- 10%. Detailed sub-domain modeling with parameter extraction is the base for the system level porous-media calculations with thermal field-coupling between solid fluid and solid solid interfaces. Furthermore, the strength and weakness of microchannel and pin fin heat transfer geometries in 2-port and 4-port fluid architectures is identified. Microchannels efficiently mitigate hot spots by distributing the dissipated heat to multiple cavities due to their low porosity. Pin fins with improved permeability and convective heat dissipation are advantageous at small power map contrast and aligned hot spots on the different tiers. Large stacks of 4 cm
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can be cooled sufficiently by the 4-port fluid delivery architecture. The flow rate is improved four times compared to the 2-port fluid manifold. The nonuniformity of the flow in case of the 4-port demands a more careful floor-planning. Furthermore optimization schemes such as hot-spot distribution, individual hot-spot heat flux adjustment, as well as hot-spot sub-millimeter dimensioning to minimize pumping power and maximize chip stack performance are proposed.