A passive mixer for 60 GHz applications in CMOS 65nm technology

A study of the feasibility of a wide band double balanced resistive mixer in the 60 GHz band is done. The device is implemented in a 65nm CMOS technology process. In this paper an approach to design an optimized version of the mixer in terms of the principal figures of merit: conversion loss, port to port isolation and noise figure is shown. The mixer will be a part of an homodyne down-conversion system. The conversion loss is 6.9 ± 0.2dB around 60GHz with a -5dBm of LO drive. The port-to-port isolation for the LO feed through is better than 41dB. The noise figure is 8.39dB. The power dissipation for the mixer depends on the LO buffer that increases the input LO power. Its power consumption is 15mW.