A scalable H.264/AVC deblocking filter architecture using dynamic partial reconfiguration

This paper presents a scalable H.264/AVC deblocking filter architecture based on FPGA using dynamic partial reconfiguration. This desirable feature of FPGAs makes it possible for different hardware configurations to be implemented during run-time. Architectural scalability to adapt to different users' requirements intelligently is demonstrated through dynamic self-reconfiguration on the reconfigurable hardware fabric. When exploiting the full capability of the proposed design, filtering operations up to four different edges at the same time can be performed resulting in significant reduction of total processing time. The architecture can easily support the required computing capability for different resolutions and frame rates of video sequences. The implemented architecture has been evaluated using Xilinx Virtex-4 ML410 FPGA board. The design can operate at a maximum frequency of 103 MHz. The reconfiguration is done through Internal Configuration Access Port (ICAP) to achieve maximum performance needed by real time applications.