Waiting cycle analysis on H.246 decoder run in PAC Duo platform

Two approaches for parallelization of H.264 decoder, data partition and function partition, are realized on a PAC Duo platform, which contains two Parallel Architecture Core Digital Signal Processors (PACDSP's). Eight baseline CIF sequences are decoded and their execution cycles and waiting cycles are examined. There are three roots hindering the performance of dual-core decoders: inter-core synchronization, resource contention, and cache miss. Through the waiting cycle analysis, the major reasons causing the degradation of dual core H.246 decoders are found. The inter core synchronization and resource contention principally slow down the execution speed of the dual core with function partition and dual core data partition, respectively. The precious experience and analysis will help the software and hardware designers explore the mechanisms to improve performance of the multi core scenarios.