3D image segmentation implementation on FPGA using the EM/MPM algorithm

In this paper, 3D image segmentation is implemented on Field Programmable Gate Array (FPGA) hardware. Segmentation is performed using the EM/MPM Bayesian algorithm. This algorithm segments 3D images using neighboring pixels in a Markov Random Field (MRF) clique. We have implemented this iterative algorithm in Xilinx FPGA, and have achieved greater than 100 times improvement over standard desktop computing hardware. Key to achieving this speed are: a pipelined, parallel data path structure and a novel memory interface for solving the external memory bandwidth problem.