Chip embedding technology developments leading to the emergence of miniaturized system-in-packages

At PCB manufacturing level, 50 μm thin chips have been embedded with pitches up to 200 μm in up to 18”x24” panels. This paper shows the further developments in chip embedding technologies to incorporate chips with even smaller pitches. The technology developed in this study does not necessitate expensive redistribution layers for enlarging the pad pitch. Embedding of small pitch chips has been realised with concurrent developments in accurate chip positioning, plating methods and chemistries and ultra fine line patterning. The results in this paper show the emergence of a new prototype Embedded chip-QFN package with contact pads at 400μm pitch and a total number of 84I/Os with dimensions of 10mm×10mm. The embedded chip in the QFN package is 5mm×5mm in size and has a peripheral pad configuration at 100μm pitch. All Embedded chip-QFN packages have been manufactured in 10”x14” panels at prototype level. This paper also addresses all challenges for semi-additive processes for copper structuring of chip embedded packages with pitches lower than 100μm. Qualitative analysis using acoustic microscopy and shear testing of the QFNs provides evidence of good resin adhesion and package mechanical robustness. This study shows promising results for embedding of chips with different contact pitches through alternative embedding strategies and in conjunction with developments for very dense copper routing, it provides strong evidence for the manufacturability of highly miniaturised embedded chip system-in-packages with a total thickness of 160μm.