Segmented tri-gate bulk CMOS technology for device variability improvement

Tri-gate bulk MOSFETs are realized using a simple shallow-trench-isolation (STI) oxide recess approach. The tri-gate structure together with a retrograde body doping profile provides for superior electrostatic integrity, particularly for narrow fin widths, to reduce variability in transistor performance. The benefits of tri-gate bulk MOSFET technology for 28 nm-node 6-T SRAM cells (0.149 um
²
bit-cell area) are assessed. As compared against planar cells, tri-gate cells show less degradation in static noise margin (SNM) and write margin (WRM) variations with decreased operating voltage. Thus, the STI-recess process provides a simple means for reducing device performance variability to facilitate CMOS technology scaling.