A novel TCAD-based methodology to minimize the impact of parasitic structures on ESD performance

During an ESD event, breakdown of a parasitic bipolar transistor can lead to chip failure. For a variety of ESD protection networks, it is demonstrated that TCAD simulations correctly predict the stress level at which failure occurs due to bipolar breakdown. A procedure to characterize the interaction between any two N-type diffusions and the ESD cells to which they are connected is presented.