Adaptive tuning of sparse matrix-vector multiplication on Cell architecture

Sparse matrix-vector multiplication is a kernel which is widely used in scientific applications. The sparse-data is usually stored in the compressed row storage format, which introduces the irregular reference pattern. It's a problem for the software cache on Cell architecture because the software cache line is always set to a specific size in traditional software cache strategies, which limits cache utilization and increases memory bandwidth overhead. In this paper, we propose an adaptive cache line strategy which continuously adjusts cache line size during SpMV multiplication execution. Therefore, the transferred data size and the execution time are significantly decreased. Moreover, a prefetching scheme is proposed to further improve performance. The evaluation indicates that our adaptive cache line scheme achieves a speedup factor from 2.11 to 3.57 compared to the traditional software cache approach. And the prefetching approach translates into speedup factor up to 3.2 for the SpMV multiplications.