An innovative FPGA internal core clock jitter prediction methodology

Adances in nanotechnology have so far met the market demand of high-speed electronic system applications. However, the high-speed applications give rise to high noise spectrums and make the system designs complicated. As a result, the design complexity causes the power delivery network (PDN) to be susceptible to noise. An increase of noise in a PDN induces an increase of jitter and causes severe degradation of the timing margin in an electronic system implementation. Various studies have been carried out in modeling and reducing noise induced in the PDN. However, studies on device internal core clock jitter (iCCJ) effect due to the PDN noise are still in their infancy. This paper presents an innovative methodology of predicting device iCCJ based on the charge-per-clock-cycle concept and resonance condition. The innovative methodology shows a reasonably good correlation between the measured jitter of the various core logic patterns and the predicted result. This jitter prediction tool helps electronic system designers to estimate iCCJ resulted from core logic utilization during the Field Programmable Gate Arrays (FPGA) system prototyping phase. Consequently, jitter prediction can help to improve the system's timing margin and achieve error-free designs.