Low power, testable dual edge triggered flip-flops

Power dissipation is an important parameter in the design of VLSI circuits, and the clock network is responsible for a substantial part of it (up to 50%). Two main approaches have been suggested to reduce clock dissipation: clock gating and low power flip-flops. In this article we address the latter. We demonstrate that the usage of double edge triggered flip-flops results in a power reduction of 50% in the clock net, and in a reduction of up to 45% inside the flip-flops. Furthermore, we consider other flip-flop parameters, like setup and hold times, propagation delay and testability.