CTC Turbo Decoding Architecture for H-ARQ Capable WiMAX Systems Implemented on FPGA

This paper presents the results of a hybrid automatic request (H-ARQ) capable, convolutional turbo decoder implementation on field programmable gate array (FPGA). It emphasizes area, speed, and the decoding performances when using fixed point implementation. The convolutional turbo coding scheme is the one specified in the 802.16e-2005 standard. The code data rates are 1/2, 2/3, and 3/4, the maximum number of iterations is 8, and the block size is from 6 to 600 bytes. The maximum number of retransmissions for H-ARQ block is 4, according to the mandatory profiles of the 4G communication systems.