A 622-Mbps CMOS Bit/Frame Synchronizer for High-Speed Backplane Data Communication

A new bit/frame synchronizer with optimum clock extractor and elastic serial-to-parallel (S/P) converter is presented. The circuit selects the suitable clock from equally phased multiple clocks generated by a PLL. The elastic S/P converter not only expands the bits but also recovers the frame synchronization. By our compact circuit implementation, the total hardware amount is greatly reduced. The circuit is designed for 32-input system and can handle 622Mbps with 15mW at 3.3V power supply in a 0.5-μm CMOS process technology.