A High Speed Wide Band SRAM Macro using Complementary Half-Swing Bus Architecture

A complementary half swing architecture is proposed for the high speed and low power bus operation. The bus is composed from a pair of lines. Each bus line within a pair utilizes the upper or lower half of the supply voltage exclusively. The architecture is applied to an embedded SRAM of the 0.5μm CMOS ATM switch LSI. Simulation results indicate that it operates beyond 200MHz at the supply voltage of 3.0V. The worst case power dissipation is reduced by half and the peak current is reduced by 66%.