A CMOS activity detector for ADSL link

A CMOS activity detector, integrated into a CMOS 0.7u analog front-end, is used to reduce the sleep mode power dissipation of an ADSL link (Asymmetric Digital Subscriber Line). A dynamic analog sensor using correlated double sampling permits to reach the high sensitivity of 1.5mVpp, with more than 20 dB DC and POTS (Plain Old Telephone Signal) signals rejection. In sleep mode, only the activity detector has to be powered, consuming 6.2 mW. This permits to spare the 5-6 Watts needed if all the ADSL Asics were permanently on.