Dithering of First-Order Sigma-Delta Modulators

A new dithering method to remove pattern-noise peaks in ΣΔ modulators is presented. In the new method, the digital decimation filter is matched to the dither which results in total elimination of the dither power. With respect to existing dithering techniques, the decrease in dynamic range inside the loop filter is negligible because little dither power is required (≪30% FS). Experiments with a transducer interface IC in a 3μm BiCMOS technology prove good agreement with the theory. Adding only little hardware results in an improvement in the integral non-linearity from 13 bits to the 16 bits level.