Time-Interleaved Sampled-and-Hold S2I Circuit for High-Speed Current-Mode ADCs

This paper describes a current-mode sample-and-hold circuit which comprises two time-interleaved S
²
I cells and is capable of operating under loading conditions appropriate for high-speed current-mode analogue-to-digital converters. A prototype integrated circuit fabricated in a 1.2 μm digital CMOS technology exhibits better than 8-bits linearity at 25 MHz sampling frequency. At 5 V supply it dissipates less than 1.5 mW.