A 17 nS, 100 nA Stand-by Current Full CMOS 1 Mbit SRAM

A 17 ns, 100 nA stand-by current, full CMOS, 1 Mbit SRAM has been developed. It was fabricated using a 0.5 um, double poly, double metal technology. The use of a full bulk CMOS 6 T memory cell allows a very low stand-by consumption. The low operating power is obtained thanks to a hierarchical architecture. A full differential data path provides a good noise immunity and a fast access time. The memory cell area is 7.15 * 6.5 um
²
with a chip size of 5.41 * 15.85 mm
²
. The typical performances are a chip select access time of 16.5 ns, a stand-by current of less than 100 nA and an operating consumption of 120 mA for a 50 MHz cycle.