Deep Sub-Micron BICMOS Circuit Technology for Sub-10 ns ECL 4-Mb DRAMs

Alternatives for on-chip voltage limiters and direct sensing schemes were evaluated in terms of ease of design, voltage margins and speed. Based on these evaluations, a 0.3μm ECL 4Mb BiCMOS DRAM was designed with a simulated access time of 7.8ns. It incorporates a voltage limiter featuring connection to VCC terminals, a BiCMOS output stage and use of a band-gap reference scheme, and a direct sensing scheme combined with a one-stage MOS amp. Through an analysis of access time dependence on device parameters, severe control of MOS transistor parameters proved to be a great importance in obtaining high speed DRAMs.